The present invention relates broadly to signal processing and, more particularly, to interfacing with a variety of multimedia signals.
Field programmable logic and in particular, field programmable gate arrays (FPGAs), have become the solution of choice for logic design implementation in applications where time to market is a critical product development factor. In addition, such reconfigurable arrays have been used to enhance customer product flexibility in ways that no other technology can currently match.
Microprocessors have traditionally been used to satisfy time to market and end product flexibility needs. This solution may not meet performance constraints and lacks the concurrency possible in an unconstrained hardware design. Typical design processes, therefore, reach a point where the overall design is partitioned into hardware and software components. An interface is defined and the design process continues along two parallel paths. Sometime later, the software and hardware components must be integrated. Problems usually develop at this point because of interface misinterpretation or partitioning that cannot meet design requirements. This impacts the hardware, the software and the schedule. If the hardware design is realized in programmable logic, the hardware can be manipulated as easily as the software.
Products which adapt to the end user""s particular requirements, through self-directed or end user directed reconfiguration, are becoming more prevalent. As the number of modes of operation increases, mode-specific hardware becomes a less cost-effective solution. In the case where the end user is truly directing the adaptation, predetermined hardware solutions become unacceptable. Reconfigurable logic enables design solutions where dynamic hardware/software re-partitioning is possible.
Programmable logic not only vastly improves the time necessary to implement a static design, but significant time to market and product feature benefits can be realized when hardware can dynamically be altered as easily as software.
To reduce design cycles, designers have also turned towards high level design languages (e.g., HDL) and logic synthesis tools. Many programmable logic solutions are poorly suited to this design methodology, however. An incompatibility exists between logic synthesis algorithms originally developed for gate-level design and the block-like structures found on many programmable logic devices. This can result in significant under utilization or degraded performance. In either case a more expensive device is required. Real gate-level programmable devices are ideally suited to this design methodology.
When schematic-based design methods are used, some programmable logic solutions impose significant constraints on design implementation to ensure satisfactory results. This imposition tends to bind the design to a particular programmable device and requires a significant learning investment. Any design specification changes which impact design decisions made to fit this imposed structure can have disastrous effects on utilization and performance and can potentially require a more expensive device or even a costly redesign. Gate-level programmable devices, coupled with sophisticated, timing-driven, implementation tools, minimize device-specific optimization.
Any design process includes a significant amount of learning. Usually engineers spend most of this time learning about product requirements or prototyping critical portions of the design to prove implementation feasibility. Many programmable logic solutions are not xe2x80x9cpush buttonxe2x80x9d. Time must be spent learning programmable device architecture or implementation tool quirks. Worse yet, the design may require modification or manual component placement to meet design targets. This increases the cost and time to market.
The discipline of multimedia signal processing typifies the challenges discussed hereinabove. Various emerging and evolving multimedia standards continue to create substantial confusion in the design of appropriate IC (and systems incorporating ICs) architecture(s). The current xe2x80x9csolutionsxe2x80x9d to these problems can broadly be characterized as:
dedicated multiple chipsets, along with some number of interface chips; and
programmable engines, specific to a particular standard, along with some number of interface chips.
Each of these xe2x80x9csolutionsxe2x80x9d requires multiple chips, and either a very expensive custom system/board combination of chips for each application or an inefficient use of multiple chips to meet a specific application. Hence, there is a need for a solution to facilitate multimedia system or subsystem design using a single IC chip which is adaptable (or readily configurable) to a variety of standards.
The following documents, all of which are US patents, all of which are incorporated by reference herein, disclose various techniques having some relevance to the present invention.
U.S. Pat. No. 5,696,959 (December 1997) discloses memory store from a selected one of a register pair conditional upon the state of a selected status bit.
U.S. Pat. No. 5,696,954 (December 1997) discloses three input arithmetic logic unit with shifting means at one input forming a sum/difference of two inputs logically ANDed with a third input logically ORed with the sum/difference logically ANDed with an inverse of the third input.
U.S. Pat. No. 5,680,339 (October 1997) discloses method and rounding using redundant coded multiply result. See also U.S. Pat. No. 5,644,522 (July 1997) which discloses method, apparatus and system for multiply rounding using redundant coded multiply result.
U.S. Pat. No. 5,644,790 (July 1997) discloses a universal CD ROM interface using single interface connection.
U.S. Pat. No. 5,644,524 (July 1997) discloses an iterative division apparatus, system and method employing left most one""s detection and left most one""s detection with exclusive OR.
U.S. Pat. No. 5,625,836 (April 1997) discloses SIMD/MIMD processing memory element (PME).
U.S. Pat. No. 5,606,677 (February 1997) discloses a packet word multiply operation forming output including most significant bits of product and other bits of one input.
U.S. Pat. No. 5,603,012 (February 1997) discloses a start code detector.
U.S. Pat. No. 5,600,847 (February 1997) discloses a three input arithmetic logic unit with mask generator. See also related U.S. Pat. No. 5,590,350 (December 1996).
U.S. Pat. No. 5,590,345 (December 1996) discloses an advanced parallel array processor (APAP). See also related U.S. Pat. No. 5,588,152 (December 1996) which discloses an advanced parallel processor including advanced support hardware.
U.S. Pat. No. 5,577,213 (November 1996) discloses a multi-level adaptor card for computer.
U.S. Pat. No. 5,522,082 (May 1996) discloses a graphics display processor, a graphics display system and method of processing graphics data with control signals connected to a central processing unit and graphics circuits.
U.S. Pat. No. 5,512,896 (April 1996) discloses a Huffman encoding method, circuit and system employing most significant bit change for size detection,
U.S. Pat. No. 5,511,211 (April 1996) discloses a method for flexibly developing a data processing system comprising rewriting instructions in non-volatile memory elements after function check indicates failure of required functions.
U.S. Pat. No. 5,504,920 (April 1996) discloses a video driver system for communicating specific primitive commands to multiple video controller types.
U.S. Pat. No. 5,479,166 (December 1995) discloses a Huffman encoding method, circuit and system employing conditional subtraction for conversion of negative numbers.
U.S. Pat. No. 5,404,555 (April 1995) discloses a macro instruction set computer architecture.
U.S. Pat. No. 5,379,388 (January 1995) discloses digital signal processing apparatus with sequencer designating program routines.
U.S. Pat. No. 4,744,054 (May 1988) discloses a semiconductor device with a memory circuit.
Unless otherwise noted, or as may be evident from the context of their usage, any terms, abbreviations, acronyms or scientific symbols and notations used herein are to be given their ordinary meaning in the technical discipline to which the invention most nearly pertains. The following terms, abbreviations and acronyms may be used in the description contained herein:
A/D: Analog-to-Digital (converter).
ALU: Arithmetic Logic Unit.
ASIC: Application-Specific Integrated Circuit.
bit: binary digit.
byte: eight contiguous bits.
CAM: Content-Addressable Memory.
CMOS: Complementary Metal-Oxide Semiconductor.
CODEC: Encoder/De-Coder. In hardware, a combination of A/D and D/A converters. In software, an algorithm pair.
CPU: Central Processing Unit.
D/A: Digital-to-Analog (converter).
DRAM: Dynamic Random Access Memory
DSP: Digital Signal Processing (or Processor)
EEPROM: Also E2PROM. An electrically-erasable EPROM.
EPROM: Erasable Programmable Read-Only Memory.
Flash: Also known as Flash ROM. A form of EPROM based upon conventional UV EPROM technology but which is provided with a mechanism for electrically pre-charging selected sections of the capacitive storage array, thereby effectively xe2x80x9cerasingxe2x80x9d all capacitive storage cells to a known state.
FPGA: Field-Programmable Gate Array
g: or (giga), 1,000,000,000
Gbyte: gigabyte(s).
GPIO: General Purpose Input/Output.
HDL: Hardware Description Language.
IC: Integrated Circuit.
I/O: Input/Output.
IEEE: Institute of Electrical and Electronics Engineers
JPEG: Joint Photographic Experts Group
k: (or kilo), 1000.
KHz: KiloHertz (1,000 cycles per second).
MAC: Media Access Control.
Mask ROM: A form of ROM where the information pattern is xe2x80x9cmaskedxe2x80x9d onto memory at the time of manufacture.
MCM: Multi-Chip Module.
memory: hardware that stores information (data).
M: (or mega), 1,000,000
MHz: MegaHertz (1,000,000 cycles per second).
MLT: Multi-Level Technology.
NVRAM: Non-volatile RAM.
PLL: Phase Locked Loop
PROM: Programmable Read-Only Memory.
PWM: Pulse Width Modulation.
PLD: Programmable Logic Device.
RAM: Random-Access Memory.
RISC: Reduced Instruction Set Computer (or Chip).
ROM: Read-Only Memory.
SIE: Ser. Interface Engine.
software: Instructions for a computer or CPU.
SRAM: Static Random Access Memory.
UART: Universal Asynchronous Receiver/Transmitter.
USB: Universal Ser. Bus.
UV EPROM: An EPROM. Data stored therein can be erased by exposure to Ultraviolet (UV) light.
VHDL: VHSIC (Very High Speed Integrated Circuit) HDL.
An object of the present invention is to provide a multimedia subsystem capable of being adapted to multiple disparate multimedia standards.
Another object of the invention is to provide such a multimedia subsystem on a single IC chip.
According to the invention, a single integrated circuit (IC) chip has a block of user-programmable (reconfigurable) logic such as a field-programmable gate array (FPGA), and has a multimedia processor xe2x80x9ccorexe2x80x9d (functional block). These two blocks are combined (integrated) on a single IC chip to provide an off-the-shelf, semi-customizable component for multimedia applications.
In addition to the processor core and reconfigurable logic blocks, one or more of the following additional cores may be also be integrated onto the IC:
audio and/or video CODECs for interfacing to external analog multimedia signals;
phase locked loop (PLL) circuitry to reduce skew within various blocks within the IC chip and to synchronize to off-chip clock circuitry;
a programmable, fast serial interface core;
a programmable CPU interface core;
a programmable memory interface (PMI) core; and
power-down circuitry, in combination with one or more of these additional cores, to provide power and/or processing savings when a given one of the cores is not in use.
A benefit of incorporating at least a media processor and reconfigurable logic onto a single IC chip, according to the invention, is that it is the hardware itself that can be configured to accommodate disparate multimedia standards, rather than requiring instructions (software) to be fed to the processor. This has a marked advantage in speed and density, and power.
According to an aspect of the invention, specific multimedia standards can be incorporated in and accommodated by (e.g., implemented by the programmable logic of) the IC chip of the present invention, including, but not limited to JPEG, MJPEG, MPEG-1, MPEG-2 with various levels and profiles, as well as video conferencing standards such as H.263, as well as specific serial standards such as IEEE 1394 or USB.
An integrated circuit (IC) employing the techniques of the present invention may be included in a system or subsystem having electrical functionality. Example systems may include general purpose computers; telecommunications devices (i.e., phones, faxes, etc.); networks; consumer devices; audio and visual receiving, recording and display devices; vehicle; etc. It is within the scope of the invention that such systems would benefit substantially from technique(s) of the present invention.
Other objects, features and advantages of the invention will become apparent in light of the following description thereof.